Liquid crystal display units used for certain applications such as projectors (PJ) and head-up displays (HUD) are requested to have a small display size, in order to make the size of expensive optical components, such as a lens and a prism, smaller. Simultaneously, such liquid crystal display units are further requested to cope with image quality deterioration due to irradiation of light since those liquid crystal display units are irradiated with extremely strong light for a purpose of forming a bright image. In order to respond to the above requests, many of the liquid crystal display units used for the above applications are manufactured by a polycrystalline-silicon thin-film transistor process or a poly-Si TFT process. As the reasons, the following points may be assumed. First, poly-Si TFTs have a field-effect mobility larger by 100 or more times than that of amorphous-silicon thin-film transistors (a-Si TFTs). Constituting a peripheral circuit of a liquid crystal display unit by using poly-Si TFTs can make the liquid crystal display unit small. Further, poly-Si TFTs have light sensitivity lower than that of a-Si TFTs. Accordingly, poly-Si TFTs are not likely to cause image quality deterioration due to a light leakage current. Generally, if a light leakage current takes place in a pixel TFT, a pixel voltage tends to fluctuate, which causes lowering of contrast and flicker.
However, even in the case where poly-Si TFTs are used in such liquid crystal display unit, if the poly-Si TFTs are irradiated with light with an illuminance of millions or more lux as in a projector (PJ), a light leakage current in the poly-Si TFTs cannot be ignored. Since the poly-Si TFTs have a planar type structure, a channel section of each TFT is directly irradiated with light via a glass substrate, which may become one of the causes of the light leakage current. In order to cope with the above problem, Japanese Unexamined Patent Application Publications (JP-A) No. H02-15676 proposes a technique to reduce a light leakage current in such TFTs.
FIG. 12 shows a cross-sectional constitution of a poly-Si TFT disclosed in JP-A No. H02-15676. On a TFT substrate 101, a light shielding film 320 made of a high melting point metal or its oxide is disposed beneath a polycrystalline silicon film 340 across an interlayer film 330. Further, a gate insulating film 350, a gate electrode 360, an interlayer film 370 and a wiring metal 380 are formed on the polycrystalline silicon film 340. In a pixel section using a TFT having the above structure, a TFT channel section beneath a gate electrode 360 is not irradiated directly with light from the TFT substrate 101 side, whereby it becomes possible to reduce a light leakage current in a TFT greatly. The above structure is mainly applied to TFTs in a pixel section, and is not applied to TFTs in a peripheral circuit section. This is because a light shielding film which is disposed beneath a TFT channel section and has conductivity can cause fluctuation in the threshold voltage of the corresponding TFT. In a TFT in the pixel section, a voltage applied between a source and a drain is lower than a voltage applied between a source and a gate. Accordingly, even if the above fluctuation of the threshold voltage occurs, the TFT operates normally. On the other hand, in a TFT in the peripheral circuit section, in many cases, a voltage between a source and a drain and a voltage between a gate and a source are equal to each other. Accordingly, characteristics of the circuit fluctuate due the fluctuation of the threshold voltage, which causes lowering of the output voltage of the peripheral circuit section and malfunction.
Therefore, for the peripheral circuit section, a method has been proposed so as to shield it from light with a package member. FIG. 13 is a cross-sectional view of a liquid crystal display module for a projector disclosed in JP-A No. H06-202160 (corresponding to US2003/0025659A1). The liquid crystal display module includes a liquid crystal panel composed of a TFT substrate 101, a CF substrate 102, liquid crystal 103 and a sealing member 104, and is structured such that the peripheral portion of the liquid crystal panel is covered with a package member 106 made of a material which does not transmit light, such as a black mold resin or a ceramic. The package member 106 is provided with an opening section 107 through which a pixel matrix 200 can be irradiated with light. On the other hand, a peripheral circuit 105 is arranged at a position covered with the package member 106, whereby the peripheral circuit 105 is not affected by light.
Although the problem caused by a light leakage current of a TFT is improved by the above-mentioned method, another problem arises in that the cost of a liquid crystal display module becomes high. The reason is described below. According to the above-mentioned method, it is necessary to prepare a liquid crystal display module in which a pixel section (pixel matrix) is not covered with a package member and a peripheral circuit is covered with the package member. Therefore, if a distance between the pixel section and the peripheral circuit in the liquid crystal panel is small, it is required to assemble the liquid crystal panel and the package member with extremely high accuracy. However, the outside dimension of the liquid crystal panel includes a tolerance in a cutting process, and the dimension of the package member also includes a tolerance. Furthermore, a tolerance takes place also in a process of superposing the liquid crystal panel and the package member. Each of the above tolerances is about 0.2 mm to 0.5 mm. In order to surely prepare a structure that the pixel section is not covered with the package member and the peripheral circuit is covered with the package member, each of the distance M1 and the distance M2 in FIG. 13 is required to have a value equal to or larger than the total of the above tolerances, and each of the distances M1 and M2 usually becomes about 1 mm, where M2 represents a distance from an edge of the pixel matrix 200 to an edge of the opening section 107 of the package member 106, M1 represents a distance from an edge of the opening section 107 of the package member 106 to an edge of the peripheral circuit 105. Accordingly, a necessary distance from the edge of the pixel matrix 200 to the edge of the peripheral circuit 105 becomes about 2 mm. In a liquid crystal panel including peripheral circuits 105 arranged at both sides of the pixel matrix 200, functionless areas extending over a total length of 4 mm need to be secured, which enlarges the liquid crystal panel. If the external shape of a liquid crystal panel becomes large, the number of substrates of liquid crystal panels which can be laid out in one mother substrate decreases. Therefore, especially, in the case of a liquid crystal panel for a head-up display, whose display area has a diagonal dimension being about 2 inches and is larger than that of a liquid crystal display unit for a projector, the reduction of the number of substrates which can be laid out in one mother substrate becomes extremely large, which increases cost.
As a method of solving the above problems, the method disclosed by JP-A No. 2008-165029 may be used. In this method, a light shielding film is arranged for each of TFTs in a pixel section and TFTs in a peripheral circuit, wherein an earth potential is applied to the light shielding film for each TFT in the pixel section and a gate potential is applied to the light shielding film for each TFT in the peripheral circuit. According to this method, there is no need to surely cover the peripheral circuit with a light shielding package member, and a panel size can be made small.
Further, as a technique to lower the cost of a liquid crystal display unit, for example, as disclosed by JP-A No. 2006-351165 (corresponding to US2006/0262074A1), a method of forming TFTs in a pixel section and TFTs in a peripheral circuit to be poly-Si TFTs of a single conductivity type may be used. FIG. 14 shows a circuit diagram of a gate driver constituted by p-type poly-Si TFTs, which is disclosed in JP-A No. 2006-351165, where Tr1 to Tr8 represent transistors, IN represents input signal, OUT represents output signal, CL1 and CL2 represent clock signal, RST represents reset signal, VDD represents a power source, VSS represent the ground, and N represents a node.
In the case where the light shielding method for TFTs disclosed in JP-A No. 2008-165029 is combined with the method of constituting a peripheral circuit with poly-Si TFTs of a single conductivity type disclosed in JP-A No. 2006-351165, an area necessary for forming a peripheral circuit increases greatly. As a result, it turns out by the inventor's investigation that the panel size is hardly miniaturized. The reasons are described below.
In the method disclosed in JP-A No. 2008-165029, a light shielding film disposed beneath each TFT constituting the peripheral circuit is needed to be provided with the same electric potential with a gate electrode of the corresponding TFT. In an example of the circuit shown in FIG. 14, eight TFTs are used in one block constituting a scanning circuit, where a gate-electrode electric potential is common to both of TFTs Tr1 and Tr2, a gate-electrode electric potential is common to both of TFTs Tr3 and Tr4, and similarly, a gate-electrode electric potential is common to both of TFTs Tr7 and Tr8. In consideration of the above situations, the light shielding films are provided as at least five separated island-shaped films each independent electrically from the others. FIG. 15 is a layout diagram showing a single TFT including a contact hole 325 adapted to connect a gate electrode 360 and a light shielding film 320, and FIG. 16 shows a cross-sectional view taken along the line XVI-XVI in FIG. 15. In FIGS. 15 and 16, 101 represents a TFT substrate, 330 and 370 represent interlayer films, 340 represents a polycrystalline silicon film, 350 represents a gate insulating film, 360 represents a gate electrode, and 380 represents wiring metal. In the example shown in here, the light shielding film 320 is electrically connected with the gate electrode 360 through the contact hole 325 which penetrates the interlayer film 330 and the gate insulating film 350. That is, it is necessary to form such a contact hole 325 in each of the light shielding films being the five separated island-shaped films. Accordingly, an area needed to constitute the circuit increases greatly. Since a gate driver for one block is needed to be arranged within the same width as a pixel pitch, an amount of an increase in a circuit area becomes appreciably larger in a liquid crystal display unit with a small pixel pitch.
Further, in a liquid crystal panel in which the circuit is constituted with TFTs of a single conductivity type, a bootstrap method is used such that the amplitude of an output voltage may become equal to a power source voltage. In the circuit shown in FIG. 14, the gate potential of TFT Tr7 is lowered by the bootstrap method (in the case of using p-type TFTs), and it operates such that the amplitude of output signal OUT becomes equal to the voltage between power sources VDD and VSS. If describing a little in more detail, in the bootstrap method, first, the electric potential of a node N connected to the gate of TFT Tr7 is made to an electric potential to make TFT Tr7 become a conduction state. Thereafter, the node N is made into a floating state, and clock signal CL1 transits to a low level, whereby the electric potential of the node N lowers together with an electric potential change of a source potential (OUT) by a capacitive coupling between a source and a gate of TFT Tr7. Here, if the method disclosed in JP-A No. 2008-165029 is applied to this circuit, a light shielding film which overlaps with the source and drain regions of TFT Tr7 in a planar view is disposed beneath the TFT Tr7, and the light shielding film is connected to a gate electrode electrically. Accordingly, the parasitic capacitance of the node N becomes extremely large. This is because TFTs Tr6 and Tr7 are constituted to form an output section in this circuit and the channel width of TFT Tr7 is set to become extremely large in order to charge and discharge a gate line of a pixel region serving as a load within a given time period. If the parasitic capacitance of the node N is large, it takes a long time to provide the node N with an electric potential to make TFT Tr7 to a conduction state. Accordingly, another problem arises in that a high speed operation cannot be performed. Even if the peripheral circuit is constitute with n-type TFTs, these problems occur similarly.
The present invention seeks to solve the problems.